1. Field of the Invention
The present invention relates to a flat panel display device, and more particularly, to a bi-directional driving circuit of a flat panel display device and method for driving the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for enabling a bi-directional driving without an additional input pad and an input signal.
2. Discussion of the Related Art
A typical liquid crystal display (LCD) device includes a driving circuit in an LCD panel, such as a gate driving integrated circuit (IC) and a data driving IC. Also, the LCD device has a fixed driving direction, so that system manufacturers sometimes require various panels according to a related art.
FIG. 1 is a circuit diagram of a related art liquid crystal display (LCD) panel.
Referring to FIG. 1, a polysilicon thin film transistor (TFT) LCD panel includes a pixel array having a plurality of gate lines G1 to Gm arranged to cross a plurality of data lines D1 to Dn, a plurality of first shift registers 11 and first buffers 12 supplying scan signals to each gate line, a plurality of second shift registers 13 and second buffers 14 driving the data lines respectively located in each block of the ‘k’ blocks divided from each data line, a plurality of signal lines S1 to Sn transmitting video signals output from a digital-to-analog converter 5 of a data driving circuit 2 to each data line, and a plurality of switching elements 16 sequentially applying the video signals of the signal lines S1 to Sn to the data lines per each block by using the driving signals output from the second shift registers 13 and second buffers 14.
Unlike the conventional amorphous silicon circuit, in the driving circuit of the polysilicon TFT LCD panel, the data lines are divided into ‘m’ blocks while the gate lines are selected, thereby reducing the number of contact lines between an external circuit and a panel, so that a display voltage is sequentially supplied to the data lines. Therefore, the gate lines and the data lines are sequentially driven by the shift registers to display picture images. In this case, since the shift registers implement shifting only in a fixed direction, a degree of freedom in a driving direction required by system manufacturers is very limited.
A shift register of the related art LCD panel will be described with reference to FIG. 2.
FIG. 2 is a circuit diagram of the shift register of the related art LCD panel.
A gate pulse or a data start pulse Vst, first to fourth clock signals CLK1, CLK2, CLK3, and CLK4 of different phases, and first and second power source voltages Vdd and Vss are input to an input terminal of the shift register.
The circuit structure of the shift register includes eight blocks having a similar structure to one another except for the location where a clock signal is applied.
The first block includes a first p-MOS transistor TFT1, a second p-MOS transistor TFT2, a third p-MOS transistor TFT3, a fourth p-MOS transistor TFT4, a fifth p-MOS transistor TFT5, a sixth p-MOS transistor TFT6, and a seventh p-MOS transistor TFT7.
The first p-MOS transistor TFT1 has source and gate terminals to which the start pulse Vst is applied. The second p-MOS transistor TFT2 has a source terminal connected to a drain terminal of the first p-MOS transistor TFT1, and a gate terminal to which the fourth clock signal CLK4 is applied. The third p-MOS transistor TFT3 has a source terminal connected to a drain terminal of the second p-MOS transistor TFT2, and a drain terminal connected to the Vss terminal. The fourth p-MOS transistor TFT4 has a source terminal connected to the Vdd terminal, a gate terminal connected to the third clock signal CLK3, and a drain terminal connected to the gate terminal of the third p-MOS transistor TFT3. The fifth p-MOS transistor TFT5 has a source terminal connected to the drain terminal of the fourth p-MOS transistor TFT4, a gate terminal connected to the start pulse Vst, and a drain terminal connected to the Vss terminal. The sixth p-MOS transistor TFT6 has a source terminal connected to the first clock signal CLK1, a gate terminal connected to a drain terminal of the second p-MOS transistor TFT2, and a drain terminal connected to the output terminal. The seventh p-MOS transistor TFT7 has a source terminal connected to the output terminal, a gate terminal connected to the drain of the fourth p-MOS transistor TFT4, and a drain terminal connected to the Vss terminal.
A contact node between the drain terminal of the first p-MOS transistor TFT1 and the source terminal of the second p-MOS transistor TFT2 is connected to the Vss terminal through a first capacitor C1. The gate terminal of the sixth p-MOS transistor TFT6 is connected to the Vss terminal through a second capacitor C2. The gate terminal and the drain terminal of the sixth p-MOS transistor TFT6 are connected to one another through a third capacitor C3. The gate terminal of the seventh p-MOS transistor TFT7 is connected to the Vss terminal through a fourth capacitor C4.
The clock signals are differently applied to each source terminal of the sixth p-MOS transistor TFT6, each gate terminal of the fourth p-MOS transistor TFT4, and each gate terminal of the second p-MOS transistor TFT2, respectively corresponding to second to eighth blocks. Also, an output terminal of the previous block is connected to the source and gate terminals of the first p-MOS transistor TFT1.
In other words, the clock signals are applied to the first block to the eighth block as explained in the following description.
The first clock signal CLK1 is applied to the source terminal of each sixth p-MOS transistor TFT6 in the first block and the fifth block. The second clock signal CLK2 is applied to the source terminal of the sixth p-MOS transistor TFT6 in both the second block and the sixth block. The third clock signal CLK3 is applied to the source terminal of TFT6 in both the third block and the seventh block. The fourth clock signal CLK4 is applied to the source terminal of the sixth p-MOS transistor TFT6 in both the fourth block and the eighth block.
Further, in the first and fifth blocks, the third clock signal CLK3 is applied to the gate terminal of the fourth p-MOS transistor TFT4. In both the second and sixth blocks, the fourth clock signal CLK4 is applied to the gate terminal of the fourth p-MOS transistor TFT4. In both the third and seventh blocks, the first clock signal CLK1 is applied to the gate terminal of the fourth p-MOS transistor TFT4. In both the fourth and eighth blocks, the second clock signal CLK2 is applied to the gate terminal of the fourth p-MOS transistor TFT4.
In both the first and fifth blocks, the fourth clock signal CLK4 is applied to the gate terminal of the second p-MOS transistor TFT2. In both the second and sixth blocks, the first clock signal CLK1 is applied to the gate terminal of the second p-MOS transistor TFT2. In both the third and seventh blocks, the second clock signal CLK2 is applied to the gate terminal of the second p-MOS transistor TFT2. In both the fourth and eighth blocks, the third clock signal CLK3 is applied to the gate terminal of the second p-MOS transistor TFT2.
The operation of the aforementioned shift register of the related art LCD panel will be described as follows.
FIG. 3 illustrates input and output waveforms of the shift register of the related art LCD panel.
First, the operation of the first block will be described.
The first p-MOS transistor TFT1 is turned on when a low level start pulse Vst is input in a switch-on state. At this point, since the fourth clock signal CLK4 is input at a low level in a switch-on state, the second p-MOS transistor TFT2 is also turned on. Accordingly, the node Q becomes a low level in a switch-on state, thereby turning on the sixth p-MOS transistor TFT6 and outputting the first clock signal CLK1 to the output terminal accordingly. In addition, since a node QB is at a high level in a switch-off state, the seventh p-MOS transistor TFT7 is turned off. Thus, the Vss voltage is not applied to the output terminal.
Similarly, in the second block, since the output of the first block is at a low level, and the first clock signal is at a low level, the second clock signal CLK2 is applied to the source terminal of the sixth p-MOS transistor TFT6.
As shown in FIG. 3, the outputs are sequentially generated from the first block to the eighth block.
However, the related art LCD panel having the driving circuit has the following disadvantages.
For example, picture images can be scanned only in an originally designed direction and not in the opposite direction. In other words, the output is generated in the order of the last block to the first block and cannot be generated in the order of the first block to the last block. In this case, it is difficult to set an arbitrary direction of the LCD panel, for example, in a landscape or a portrait type orientation. Therefore, the system manufacturers require different panels, thereby limiting the use of the related art LCD panels. Also, a waveform output from each stage fails to reach a desired level, thereby causing problems in driving the related art LCD panel.